1. Field of the Invention
The present invention relates to a variable current source, and more particularly to a variable current source with a small area and a high accuracy using MOS transistors.
2. Description of Related Arts
Conventionally, a variable current source circuit of this type is used for switching MOS current sources connected in parallel as weighted current sources for a DA converter. This is done to obtain a current value as an analogue output signal by adding and subtracting the individual currents by switching digital input signals, for example, as described in Japanese Patent Application laid-open No.4-42619.
FIG. 1 is a circuit diagram showing the above-mentioned known example and illustrates a six-bit DA converter. In this example, the lower two bits are composed of weighted current sources T.sub.1, T.sub.2 and the upper four bits are composed of segment current sources I.sub.1 to I.sub.15. Each of the current sources T.sub.1, T.sub.2 and I.sub.1 to I.sub.15 is composed of a single or a plurality of unit current sources t.sub.1 connected in parallel and serving as the minimum resolution. Assuming that a current value of t.sub.1 is It.sub.1, and current values of T.sub.1, T.sub.2 and I.sub.1 to I.sub.15 are IT.sub.1, IT.sub.2, and II.sub.1 to II.sub.15, respectively, the following is defined: EQU IT.sub.1 =1.multidot.It.sub.1 (1) EQU IT.sub.2 =2.multidot.It.sub.1 (2) EQU II.sub.1 .about.II.sub.15 =4.multidot.It.sub.1 (3)
Each of current sources T.sub.1, T.sub.2, and I.sub.1 to I.sub.15 is connected to node N.sub.2 through switches ST.sub.1, ST.sub.2, and SI.sub.1 to SI.sub.15.
The operation of the circuit is described herein. Switches ST.sub.1, ST.sub.2, and SI.sub.1 to SI.sub.15 are turned on and off by digital input signals to sum the switched current values based on the values shown in equations (1) through (3) for output to node N.sub.2. For example, 5.multidot.It.sub.1 represents that switches ST.sub.1 and SI.sub.1 turn on, i.e. II.sub.1 +IT.sub.1 =5.multidot.It.sub.1, while 11.multidot.It.sub.1 represents that switches ST.sub.1, ST.sub.2, SI.sub.1, and SI.sub.2 turn on, i.e. II.sub.1 +II.sub.2 +IT.sub.1 +IT.sub.2 =11.multidot.It.sub.1. In this manner, an analogue current value can be generated in a range from zero to 63.multidot.It.sub.1.
FIG. 2 is a layout diagram of the circuit shown in the above-mentioned known example and illustrates a layout when a binary weighted current source formed of T.sub.1, T.sub.2 shown in FIG. 1 is extended to compose a binary weighted current source of four bits. The binary weighting is performed by using a single or a plurality of unit current sources t.sub.1 serving as the minimum resolution.
The above-mentioned variable current source in the prior art, however, has a disadvantage as described below.
Important characteristics when considering a variable current source are a variable amount for a total output current and a tolerance error current value for the output current. Specifically, when a current source is to be made, for example, with a current variable of 28.05 .mu.A and a tolerance error current value of less than or equal to 0.11 .mu.A, such a current source may be made with a minimum current source of equal to or lower than 0.11 .mu.A. This example will be described more specifically for each scheme of the prior art.
When a current source is to be made in a segment circuit scheme, for example, with a current variable amount of 28.05 .mu.A and a tolerance current value of 0.11 .mu.A, a desired variable current source can be obtained by setting a unit segment current value to 0.11 .mu.A and connecting 255 each of such unit segment circuits in parallel. This segment circuit scheme has an advantage that the tolerance error current value for an output current is hardly degraded even when respective current values of the 255 unit segment currents are deviated due to an error in manufacturing. This scheme, however, has a disadvantage that 255 switches are required to switch the connection of 255 current sources to thereby increase the size of a circuit and the area thereof.
When a current source is similarly to be made in a weighted circuit scheme with a current variable of 28.05 .mu.A and a tolerance current value of 0.11 .mu.A, a desired variable current source can be obtained by connecting in parallel eight current sources which have current values ranging from a minimum of 0.11 .mu.A and a multiple of two thereof (a binary series) sequentially up to 14.08 .mu.A, i.e. eight current sources with current values of 0.11 .mu.A, 0.22 .mu.A, 0.44 .mu.A, 0.88 .mu.A, 1.76 .mu.A, 3.52 .mu.A, 7.04 .mu.A, and 14.08 .mu.A. In this case, switches for switching the connection of the a current sources may be not more than eight to reduce the size of a circuit. The above-mentioned scheme, however, has a disadvantage that the tolerance current value for an output current is degraded when respective current values of the eight current sources are deviated due to manufacturing. Specifically, when a random error and an inclination error on a wafer are considered in manufacturing, the random error does not become a factor to degrade the tolerance current value if a layout of the circuit is improved, for example, by using a segment current source to compose all weighted current sources as the known example shown in FIG. 2. However, in spite of such an improvement, the tolerance current value is degraded when the inclination error occurs as shown in FIG. 2. When the above-mentioned eight bit weighted current source is considered in which the inclination error becomes greater by 1% as the weighted current source proceeds to the higher order, respective currents take values as shown in FIG. 8. In this case, the total current value of the lower seven current sources is 14.6762 .mu.A, while the current value of a current source in the most highest order is 15.0656 .mu.A. A difference in the amount between the two current values is derived as follows: EQU 15.0656-14.6762=0.3894(.mu.A) (4)
The derived value is above the tolerance error current value of 0.11 .mu.A. The value is converted to a resolution as follows: EQU log.sub.2 [{(15.0656+14.6762)/0.3894}+1].apprxeq.6.27(bit) (5)
The derived value is one substantially degraded as compared with an accuracy for an eight bit binary weighted current source.
The layout can be improved to reduce an effect of the inclination error on the resolution in a weighted circuit. In such a case, however, it is required to arrange a plurality of weighted circuits at different angles to connect respective current sources such that the inclination error is canceled, which causes a disadvantage in the form of a complicated layout and an increased area.